Publicação
Configuration of the Interlock Matrix for the ATLAS-HGTD
| dc.contributor.author | Vieira,Rui Viegas | |
| dc.contributor.institution | Faculty of Sciences | |
| dc.contributor.institution | Department of Physics | |
| dc.contributor.supervisor | Santos,Helena de Fátima Nunes Casimiro dos | |
| dc.contributor.supervisor | Augusto,José António Soares | |
| dc.date.accessioned | 2026-03-20T17:15:01Z | |
| dc.date.available | 2026-03-20T17:15:01Z | |
| dc.date.issued | 2026 | |
| dc.description | Tese de Mestrado, Engenharia Física, 2026, Universidade de Lisboa, Faculdade de Ciências | |
| dc.description.abstract | The Large Hadron Collider will undergo an upgrade aimed at increasing the luminosity delivered by the injected beams (High-Luminosity Large Hadron Collider, or HL-LHC). The increased luminosity will consequently increase the radiation levels of the beams, as well as the number of simultaneous particle collisions occurring per bunch crossing. The ATLAS experiment, along with the three other LHC experiments, will be subjected to modifications that will allow it to handle the increased luminosity. Two new detectors are being developed to improve the experiment’s capacity of identifying important collisions amidst the increase in simultaneous interactions. The Inner Tracker, or ITk, will provide a higher spatial resolution when reconstructing the trajectories, while the High Granularity Timing Detector, or HGTD, will provide complementary high-precision timing information, as well as a measure of the received luminosity. The Interlock System, a hardware safety system developed for the ITk detector, is being adapted for the HGTD to ensure the safety of its infrastructure and personnel, as well as the correct operation of the detector. The system receives signals from temperature sensors installed in the detector’s modules, as well as danger signals from external systems, and controls the associated power supplies. A hardware module, the ILK-FPGA, is the nucleus of signal routing for the system. It implements the Interlock Matrix, which defines both the signal mapping and the interlock actions to be taken by the system. The work presented in this dissertation consisted in the configuration and testing of the Interlock System for the HGTD, focusing on the ILK-FPGA module. Temperature tests were conducted to verify the system’s response to overheating sensors. The Interlock Strategy was developed for the detector, as well as its implementation with the Interlock Matrix. Finally, the Interlock System was installed and tested within a prototype experimental setup of the HGTD, the Demonstrator. | en |
| dc.format | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10400.5/117689 | |
| dc.language.iso | eng | |
| dc.subject | CERN | |
| dc.subject | ATLAS Experiment | |
| dc.subject | HGTD (acronym of High Granularity Timing Detector) | |
| dc.subject | Interlock System | |
| dc.subject | Demonstrator | |
| dc.title | Configuration of the Interlock Matrix for the ATLAS-HGTD | en |
| dc.type | master thesis | |
| dspace.entity.type | Publication | |
| rcaap.rights | openAccess |
Ficheiros
Principais
1 - 1 de 1