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Code Merging for Programmable Data Plane Virtualization

2021Dissertação de mestrado Acesso aberto
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datacite.subject.fosDepartamento de Informáticapt_PT
dc.contributor.advisorSignorello, Salvatore
dc.contributor.advisorRamos, Fernando
dc.contributor.authorSequeira, Duarte Fonseca Ribeiro
dc.date.accessioned2021-06-17T12:15:41Z
dc.date.available2021-06-17T12:15:41Z
dc.date.issued2021
dc.date.submitted2020
dc.descriptionTese de mestrado, Engenharia Informática (Arquitetura, Sistemas e Redes de Computadores) Universidade de Lisboa, Faculdade de Ciências, 2021pt_PT
dc.description.abstractRecent advances in the hardware capabilities of switching chips have enabled programmability of the data plane. The development of new network protocols and functions, which historically demanded long ASIC design lifecycles to be operated, can now happen quickly and flexibly on Programmable Data Planes (PDPs). Network administrators can directly deploy custom packet processing logic as programs (written in high-level languages such as P4) into their programmable switching ASICs. There are, however, some unresolved problems associated with current PDPs, which hinder their adoption in production networks. One such problem is that a PDP target (e.g., a switch) is currently only capable of running one program at any given time. This limitation has several important consequences. First, it constrains network administrators to write large and complex programs whenever they need to deploy multiple functionalities, which is the common case. Second, it precludes resource sharing between multiple programs, potentially written by different users, limiting resource utilization and thus impacting efficiency. Inspired by the success story of virtualization in the domain of operating systems, researchers have started proposing solutions to overcome the above issue by virtualizing PDPs. Unfortunately, existing solutions are either very inefficient or lack generality. Hence, this work aims at designing a programmable data plane virtualization platform that enables the deployment of many independently-developed P4 programs on a PDP while introducing the minimum resource overhead. We achieve virtualization at the compiler-level by merging network functionalities into a single, monolithic program, where the individual P4 programs coexist fully isolated from each other. We leverage a state-of-the-art system for code merging, P4Visor, but we improve it by extending the number and variety of P4 programs that can be virtualized, from only two to multiple, and by improving resource efficiency, specifically in the packet parsing module.pt_PT
dc.identifier.tid202693520
dc.identifier.urihttp://hdl.handle.net/10451/48616
dc.language.isoengpt_PT
dc.subjectRedes Definidas por Softwarept_PT
dc.subjectPlanos de Dados Programáveispt_PT
dc.subjectVirtualização de Redespt_PT
dc.subjecta Linguagem P4pt_PT
dc.subjectTeses de mestrado - 2021pt_PT
dc.titleCode Merging for Programmable Data Plane Virtualizationpt_PT
dc.typemaster thesis
dspace.entity.typePublication
rcaap.rightsopenAccesspt_PT
rcaap.typemasterThesispt_PT
thesis.degree.nameMestrado em Engenharia Informática (Arquitetura, Sistemas e Redes de Computadores)pt_PT

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FC-DI - Master Thesis (dissertation)